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Department of Electronics and Information Technology, Faculty of Science and Technology, Hirosaki University

PAPER

Journal, Transaction, International Conference, Technical Report (Last decade)

2024年

  • Ryota Sato, Masashi Imai, "Development of Tsugaru Dialect Dictionary Management System," Proc. SASIMI2024, pp.254-259, Mar., 2024
  • Akimasa Saito, Masashi Imai, "Evaluation of FPGA Performance in a Cryogenic Environment," Proc. SASIMI2024, pp.244-249, Mar., 2024
  • Seria Kasai, Yamato Ishida, Fumiya Sano, Tomoya Akasaka, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto, "Energy Reduction of Health Monitoring Processor by Optimizing Supply and Back-Gate Voltages with Simulated Annealing," Proc. SASIMI2024, pp.227-232, Mar., 2024
  • Atsushi Onodera, Masashi Imai, "Development of Snowfall Prediction System using X-band Weather Radar and Artificial Intelligence," Proc. SASIMI2024, pp.84-85, Mar., 2024

2023年

  • Tsujiguchi T, Imai M, Kimura S, Koiwa T, Naraoka M, Hanada H, Yamanouchi K, Kashiwakura I, Ito K, "Development of an Automatic Chronological Record Creation System Using Voice AI to Facilitate Information Aggregation and Sharing in the Event of a Disaster," Disaster medicine and public health preparedness, Vol.17, e560, Dec., 2023
  • Masashi Imai, "A Study on the Implementation of Muller’s C-element in Synchronous Circuit DesignEnvironment," IEICE Technical Report, VLD2023-79, pp.255-260, Nov., 2023 (in Japanese)
  • Akimasa Saito, Masashi Imai, "FPGA Performance Evaluation in a Cryogenic Environment," IEICE Technical Report, VLD2023-23, pp.113-118, Jul., 2023 (in Japanese)
  • Masashi Imai, "Implementation of Power-outage Tolerant VLSI System using Asynchronous Circuits," IEICE Technical Report VLD2022-86, HWS2022-57, pp.79-84, Mar., 2023 (in Japanese)
  • Taiki Niida, Masashi Imai, "Development of a Two-way Translation System between Tsugaru-ben Text and Common Japanese Text using the Transformer," IPSJ Tohoku Branch SIG Technical Report, Vol.2022-7, No.4-4, Feb., 2023 (in Japanese)
  • Takuro Kasai, Masashi Imai, "Error Detection of Hardware Trojan Computers using Outlier Detection Algorithms," IPSJ Tohoku Branch SIG Technical Report, Vol.2022-7, No.4-5, Feb., 2023 (in Japanese)
  • Mao Sakamoto, Masashi Imai, "Comparison of Circuit Design Methods Suitable for Low Voltage Environments," IPSJ Tohoku Branch SIG Technical Report, Vol.2022-7, No.4-6, Feb., 2023 (in Japanese)

2022

  • Takuro Kasai, Masashi Imai, "Error Detection and Countermeasures caused by Hardware Trojan Inserted Computers," IEICE Technical Report VLD2022-55, pp.206-211, Nov., 2022 (in Japanese)
  • Masashi Imai, Kenji Kise, Tomohiro Yoneda, "Development of ASIC Prototype Chip Evaluation System using FPGA-SoM," IEICE Technical Report VLD2022-19, pp.1-6, Nov., 2022 (in Japanese)
  • Taiki Niida, Masashi Imai, "Development of Text Translation System from Tsugaru Dialect into Common Japanese," Proc. SASIMI2022, pp.163-167, Oct., 2022
  • Takuro Kasai, Masashi Imai, "Development of Diagnosis-based Hardware Trojan Tolerate System," Proc. SASIMI2022, pp.196-197, Oct., 2022
  • 岡巧, 葛西瀬梨亜, 石田大和, 佐野文也, 今井雅, 金本俊幾, "パターン密度均一化に貢献するオンチップデカップリング容量セルの提案," DAシンポジウム2022, pp.207-211,Sep., 2022 (in Japanese)
  • Taiki Niida, Masashi Imai, "Development of Text Translation System from Tsugaru Dialect into Common Japanese," Proc. DA Symposium 2022, pp.195-200, Sep., 2022 (in Japanese)
  • Mao Sakamoto, Masashi Imai, "Comparison of Synchronous Circuits and Asynchronous Circuits under Low Voltage Environment," Proc. DA Symposium 2022, pp.126-131, Sep., 2022 (in Japanese)
  • 葛西瀬梨亜, 畠山寛, 今井雅, 黒川敦, 金本俊幾, "低消費エネルギープロセッサのSoC物理設計," 情報処理学会東北支部研究報告, Vol.2021-6, No.5-3, Feb., 2022.

2021

  • Toshiki Kanamoto, Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, "An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring," Proc. of GCCE, pp.1-2, Oct., 2021.
  • 今井雅, "あなたの津軽弁を共通語に 〜弘大×AI×津軽弁の取り組み〜" 日本放射線看護学会第10回学術集会, Sep., 2021
  • 今井雅, "あなたの津軽弁、活用します 〜弘大×AI×津軽弁プロジェクト〜" 日本実験力学会, Aug., 2021
  • Mio Maeda, Akiyo Yatagai, Masashi Imai, "Prediction of Winter Precipitation from X-band Weather Radar Observations Using Deep Learning," Proc. AOGS2021, Aug., 2021
  • Masashi Imai, "Novel Circuit Structure of Basic Standard Cells against Glitches," Proc. ASYNC2021 Fresh idea track paper, Sep., 2021.
  • Kan Hatakeyama, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Masashi Imai, Atsushi Kurokawa, and Toshiki Kanamoto, "Energy efficient RISC-V processor for portable sensor applications," Proc. SASIMI2021, Mar., 2021.
  • Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, and Atsushi Kurokawa, "Thermal design technology for non-low power hearables," Proc. SASIMI2021, Mar., 2021.
  • Masashi Imai, Yuko Sugiyama, Masatoshi Matsuzaki, Ruriko Kidachi, Chieko Itaki, Takenori Niioka, Takakiyo Tsujiguchi, Ikuo Kashiwakura, "Utilization of Tsugaru-ben with Artificial Intelligence and Inheritance Activities of Tsugaru Culture," IPSJ Tohoku Branch SIG Technical Report, Vol.2020-6, No.3-1, pp.1-6, Feb., 2021 (in Japaense)
  • Taiki Niida, Akiyo Yatagai, Masashi Imai, "A Prediction of Snowfall using Hirodai Shirakami Radar and Deep Learning," IPSJ Tohoku Branch SIG Technical Report, Vol.2020-6, No.3-2, pp.1-6, Feb., 2021 (in Japaense)
  • Taisei Arima, Tsuneo Munakata, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto, "Device Structure Estimation of Trench-IGBT Based on the Data Sheet," IPSJ Tohoku Branch SIG Technical Report, Vol.2020-6, No.1-1, pp.1-6, Feb., 2021 (in Japaense)
  • Ryo Arima, Shota Kajiya, Keita Izawa, Ryosuke Watanabe, Tomohiro Aoba, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto, "Thermal Optimization for the Trimmed Shapes of the NiCr Thin Film Resistors to Improve the Pulse Durability," IPSJ Tohoku Branch SIG Technical Report, Vol.2020-6, No.1-2, pp.1-5, Feb., 2021 (in Japaense)
  • Daiki Oikawa, Tetsuya Nomura, Sumio Tanba, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto, "Estimating Fish Weight with TOF-Camera," IPSJ Tohoku Branch SIG Technical Report, Vol.2020-6, No.1-3, pp.1-6, Feb., 2021 (in Japaense)
  • Takumi Oka, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto, "On-chip Impedance Extraction for LSI, Package and Board Cooperative Design," IPSJ Tohoku Branch SIG Technical Report, Vol.2020-6, No.1-4, pp.1-4, Feb., 2021 (in Japaense)
  • Kodai Matsuhashi, Masashi Imai, Toshiki Kanamoto, Atsushi Kurokawa, "Thermal Network Model and Analysis of Hearable Devices," IPSJ Tohoku Branch SIG Technical Report, Vol.2020-6, No.2-1, pp.1-5, Feb., 2021 (in Japaense)

2020

  • 谷田貝亜紀代, 今井雅, 前田未央, "機械学習を用いたひろだい白神レーダによる冬季降雪量推定," 日本気象学会令和2年度東北地方調査研究会, Dec., 2020
  • Masashi Imai, "Asynchronous Building Blocks and Their Application for Ultra Low Energy Devices," Proc. NOLTA2020, Nov., 2020
  • Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, and Masashi Imai, "A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis," IEICE Electronics Express, Article ID 17.20200198, [Advance publication] Released June 30, 2020
  • Tomohiro Yoneda, Masashi Imai, “Coarse Grained Versus Fine Grained Architectures for Asynchronous Reconfigurable Devices,” Proc.ASYNC2020, pp.102-110, May, 2020
  • Takumi Hatase, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto, "Studies on Image Analysis and Reducing Power Consumption Towards Maintenance-Free Sensor Nodes," IPSJ Tohoku Branch SIG Technical Report, Vol.2019-6, No.2-3, Feb., 2020 (in Japaense)
  • Kan Hatakeyama, Sumio Tanba, Atsuhi Kurokawa, Masashi Imai, Toshiki Kanamoto, "A Study on Low Power Sensor Node Communication using LoRa," IPSJ Tohoku Branch SIG Technical Report, Vol.2019-6, No.2-2, Feb., 2020 (in Japanese)
  • Sota Ito, Tsuneo Munakata, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto, "A Study on Equivalent Circuit Modeling of IGBT Towards Coupled Electro Thermal Stress Analysis for Power Module," IPSJ Tohoku Branch SIG Technical Report, Vol.2019-6, No.2-1, Feb., 2020 (in Japanese)
  • Koki Kasai, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto, "Simulation-based On-chip Capacitance Extraction Method," IPSJ Tohoku Branch SIG Technical Report, Vol.2019-6, No.1-1, Feb., 2020 (in Japanese)

2019

  • Kyota Akimoto, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Quantitative Performance Comparison of Asynchronous and Synchronous Comparators," Proc. SASIMI2019, pp.296-297, Oct., 2019
  • Koki Kasai, Atsushi Kurokawa, Masashi Imai, Toshiki Kanamoto, "Efficiency Investigation of Capacitors Mounted on Re-distribution Layers for FOWLP," Proc. SASIMI2019, pp.176-179, Oct., 2019
  • Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa, "Thermal Modeling and Simulation of a Smart Wrist-worn Wearable Device," Proc. SASIMI2019, pp.138-143, Oct., 2019
  • Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai, "A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck," Proc. MWSCAS2019, pp.1085-1088, Aug., 2019
  • Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa and Masashi Imai, "Hardware Trojan Insertion and Detection in Asynchronous Circuits," Proc. ASYNC2019, pp.134-143, May, 2019
  • Ryosuke Kasai, Koutaro Hachiya, Toshiki Kanamoto, Masashi Imai, and Atsushi Kurokawa, "Neural network-based 3D IC interconnect capacitance extraction," Proc. ICCET2019, pp.168-172, Apr., 2019
  • 岡本慎太郎, 松橋功大, 今井雅, 金本俊幾, 黒川敦, "リストウェアラブルデバイスのベルト放熱効果," 電気学会 全国大会 講演論文集, p.32, Mar., 2019
  • Akiyo Yatagai, Masashi Imai, Mio Maeda, Sachinobu Ishida, "Quality Control by Making a Database (DB) of Station Precipitation Data for APHRODITE and Product Release via the Web-Site," IPSJ Tohoku Branch SIG Technical Report, Vol.2018-9, No.A2-3, Feb., 2019 (in Japanese)
  • Shinichiro Akasaka, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Performance Improvement of Bundled-Data Asynchronous Circuit by Delay-line Design Considering Delay Variation," IPSJ Tohoku Branch SIG Technical Report, Vol.2018-9, No.B3-1, Feb., 2019 (in Japanese)
  • Junya Wajima, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Implementation of Multiple Modular Redundancy System for Disabling Hardware Trojan," IPSJ Tohoku Branch SIG Technical Report, Vol.2018-9, No.B3-2, Feb., 2019 (in Japanese)
  • Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Evaluation of Hardware Trojan Detection Method in Bundled-Data Asynchronous Circuits," IPSJ Tohoku Branch SIG Technical Report, Vol.2018-9, No.B3-3, Feb., 2019 (in Japanese)

2018

  • Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Attacks and Countermeasures of Hardware Trojan in Bundled-Data Transfer Asynchronous Circuits," Hardware Security Forum 2019, Poster session, Dec., 2018 (in Japanese)
  • N. Onizawa, M. Imai, T. Yoneda, T. Hanyu, "MTJ-based Asynchronous Circuits for Re-initialization Free Computing Against Power Failures," Microelectronics Journal 82, pp.46-61, 2018 https://doi.org/10.1016/j.mejo.2018.10.012
  • Shin-ichiro Akasaka, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Replica Delay-line Design of Bundled-Data Transfer Asynchronous Circuits based on Two-phase Handshaking Protocol," Proc. DA Symposium 2018, pp.93-98, Aug., 2018 (in Japanese)
  • Takao Suzuki, Kazuki Unno, Yuta Manabe, Kyota Akimoto, Shinichiro Akasaka, Koutaro Inaba, Junya Wajima, Masashi Imai, "Research recommendation of ADC solving system using SAT solver," DAS2018 Algorithm Design Contest, Aug., 2018
  • Masashi Imai, Takeru Nanao, Yudai Ishikawa, Koutaro Inaba, "An Efficient Implementation Method and Development of Demonstration Environment for Byzantine Fault Tolerant Systems," IEICE Technical Report, DC2018-15 (SWOPP2018), pp.13-18, Jul., 2018 (in Japanese)
  • Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda, "Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols," Proc. ASYNC2018, pp.1-8, May, 2018 (Wien)
  • Yuuta Satomi Koutaro Hachiya, Masashi Imai, Toshiki Kanamoto, Kaoru Furumi, Atsushi Kurokawa, "Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm," Proc. SASIMI2018, pp.145-148, Mar., 2018
  • Masashi Imai, Naoya Onizawa, Takahiro Hanyu, Tomohiro Yoneda, "Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing," Proc. SASIMI2018, pp.283-288, Mar., 2018
  • Kaoru Furumi, Shintaro Okamoto, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa, "Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction," Proc. SASIMI2018, pp.394-397, Mar., 2018
  • Koki Kasai, Hajime Kando, Jun Chen, Masanori Hashimoto, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto, "LSI-Package-Board Power Distribution Network Modeling for Decoupling Capacitors Optimization," IPSJ Tohoku Branch SIG Technical Report, Vol.2017-6, No.B1-1, Feb., 2018 (in Japanese)
  • Takuma Oota, Tsuneo Munakata, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto, "Thermal Analysis of PowerMOS Devices including Their Bonding Wires," IPSJ Tohoku Branch SIG Technical Report, Vol.2017-6, No.B1-2, Feb., 2018 (in Japanese)
  • Zen Narita, Koki Kasai, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto, "Adjustment Method of VDD and VTH for Low Power CMOS Circuit," IPSJ Tohoku Branch SIG Technical Report, Vol.2017-6 No.B1-3, Feb., 2018 (in Japanese)
  • Syoya Era, Koki Kasai, Masashi Imai, Atsushi Kurokawa, Toshiki Kanamoto, "Work on Temperature Dependence of Signal Propagation Delay in FPGA," IPSJ Tohoku Branch SIG Technical Report, Vol.2017-6, No.B1-4, Feb., 2018 (in Japanese)
  • Daiki Toyoshima, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Design of Tamper Resistant Asynchornous Circuit Using Random Delay Element," IPSJ Tohoku Branch SIG Technical Report,Vol.2017-6, No.B3-1, Feb., 2018 (in Japanese)
  • Takeru Nanao, Yudai Ishikawa, Toshiki Kanamoto, Atsushi Kukrokawa, Masashi Imai, "Construction of Byzantine Fault Tolerant System and Its Practicality Evaluation," IPSJ Tohoku Branch SIG Technical Report, Vol.2017-6, No.B3-2, Feb., 2018 (in Japanese)

2017

  • Toshiki Kanamoto, Koki Kasai, Masashi Imai, Atsushi Kurokawa, Masanori Hashimoto, Jun Chen, Hajime Kando, "LSI-Package-Board Power Delivery Network Modeling for Capacitor Placement Optimization at 15nm Node," Proc. DAS2017, pp.111-114, Aug., 2017 (in Japanese)
  • 葛西孝己, 今井雅, 黒川敦, 金本俊幾, 陈俊, 橋本昌宜, 神藤始, "容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築," 平成29年度電気関係学会東北支部連合大会, 2E09, Aug., 2017
  • 太田拓磨, 葛西孝己, 今井雅, 黒川敦, 金本俊幾, 宗形恒夫, "PowerMOSデバイス熱設計のためのボンディングワイヤモデルの構築," 平成29年度電気関係学会東北支部連合大会, 2E03, Aug., 2017
  • Ryo Sasaki, Toshiki Kanamoto, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa, "Estimating Walking State When Holding Object in Hand by Using Neural Network," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.2B19, Aug., 2017
  • 豊嶋太樹, 金本俊幾, 黒川敦, 今井雅, "ランダム遅延素子を用いた非同期式回路の耐タンパ性向上に関する一考察," 平成29年度電気関係学会東北支部連合大会, 1G04, Aug., 2017
  • Shintaro Okamoto, Kaoru Furumi, Masashi Imai, Toshiki Kanamoto, Atsushi Kurokawa, "Method for Mitigating Heat of 3D Stacked Memory for Small Electronic Devices," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1B17, Aug., 2017
  • Yuta Satomi, Masashi Imai, Toshiki Kanamoto, Kaoru Furumi, Atsushi Kurokawa, "Optimizing Power Distribution Network Using Multi-Objective Genetic Algorithm," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1B16, Aug., 2017
  • Kaoru Furumi, Shintaro Okamoto, Toshiki Kanamoto, Masashi Imai, Atsushi Kurokawa, "Reducing Temperature by Relocating 3D IC Structures," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1B15, Aug., 2017
  • Shinichiro Akasaka, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "A Study on Replica Delay Circuit of Bundled-Data Transfer Asynchronous Circuits," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1B10, Aug., 2017
  • Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Hardware Trojan Comparison between Synchronous and Asynchronous Circuits," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1B08, Aug., 2017
  • Ryosuke Hatsuta, Masashi Imai, Toshiki Kanamoto, Shintaro Okamoto, Atsushi Kurokawa, "Thermal-Aware Tile-Based Block Placement for 3D ICs," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1B07, Aug., 2017
  • Seira Kamiie, Toshiki Kanamoto, Masashi Imai, Shintaro Okamoto, Atsushi Kurokawa, "Modeling and Analysis for Predicting Clock Skew of Stacked Chips," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1B06, Aug., 2017.
  • Takeru Nanao, Yudai Ishikawa, Masashi Imai, "A Study on Implementation Method of Byzantine Fault Tolerant Systems," IEICE Technical Report, DC2017-17 (SWOPP2017), pp.7-12, Jul., 2017 (in Japanese)
  • H. Saito, M. Imai, T. Yoneda, "Task Scheduling based Redundant Task Allocation Method for the Multi-core Systems with the DTTR Scheme," IEICE Trans. Fundamentals, E100-A, (7), pp.1363-1773, Jul., 2017
  • Koutaro Inaba, Masashi Imai, "Hardware Trojan Insertion into Asynchronous On-chip Network Router,"IEICE Technical Report, Hardware Security, Jun., 2017 (in Japanese)
  • Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda, "MTJ-Based Asynchronous Circuits for Re-initialization Free Computing against Power Failures," Proc. ASYNC2017, pp.118-125, May, 2017
  • Koutaro Inaba, Tomohiro Yoneda, Masashi Imai, "A Study on Hardware Trojan Insertion into Asynchronous NoC Router," Proc. Async2017 Fresh ideas track paper, May, 2017
  • Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "A Study on Hardware Trojan Insertion in Asynchronous NoC Router," IEICE Technical Report A-7-1, pp.82, Mar., 2017 (in Japanese)
  • Junya Wajima, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai, "Reliability Evaluation of Multiple Core Systems using Markov Model," IEICE Technical Report D-10-3, pp.137, Mar., 2017 (in Japanese)
  • Kaoru Furumi, Masashi Imai, Atsushi Kurokawa, "Cooling Architectures using Thermal Sidewalls, Interchip Plates, and Bottom Plate for 3D ICs," Proc. ISQED2017, Mar., 2017
  • Ryuhei Tachika, Toshiki Kanamoto, Masashi Imai, "Realization of High Performance Asynchronous Circuit Under Ultra Low Voltage Environment," IPSJ Tohoku Branch SIG Technical Report, Vol.2016-6 No.B1-4, Feb., 2017 (in Japanese)
  • Tatsuya Ishikawa, Toshiki Kanamoto, Masashi Imai, "Realization of Low Noise Asynchronous Circuit by Handshake Circuit Multiplexing," IPSJ Tohoku Branch SIG Technical Report, Vol.2016-6 No.B1-3, Feb., 2017 (in Japanese)
  • Komei Masukawa, Masashi Imai, Toshiki Kanamoto, "Experimental Evaluation of FPGAs Performance Variation using Multistage Ring Oscillator," IPSJ Tohoku Branch SIG Technical Report, Vol.2016-6 No.B1-2, Feb., 2017 (in Japanese)
  • Kentaro Taki, Masashi Imai, Toshiki Kanamoto, "A Study on Minimizing Energy Consumption in Ultra-Low Voltage Circuits," IPSJ Tohoku Branch SIG Technical Report, Vol.2016-6 No.B1-1, Feb., 2017 (in Japanese)

2016

  • Koutaro Inaba, Masashi Imai, "非同期式回路に対するハードウェアトロイ挿入に関する一考察," Hardware Security Forum 2016 Poster Session, Dec., 2016 (in Japanese)
  • Daiki Toyoshima, Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai, "Random Delay Elements for Tamper Resistant Asynchronous Circuits based on 2-phase Handshaking Protocol," Proc. SASIMI2016, pp.113-118, Oct., 2016
  • Masashi Imai, Tomohiro Yoneda, "Hardware Trojan Insertion Difficulties into Synchronous and Asynchronous Circuits," Proc. SASIMI2016, pp.213-218, Oct., 2016
  • Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda, "The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs," Proc. NOCS2016, pp.64-69, Sep., 2016
  • Takeru Nanao, Atsushi Kurokawa, Masashi Imai, "A Study on Byzantine Fault Tolerant Systems using SCore Cluster System Software," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), 2A07, Aug., 2016
  • Kyohei Terayama, Masashi Imai, "Scan Test of Latch-Based Asynchronous Circuits," IEICE Trans. A Vol.J99-A, No.8, pp.298-308, Aug., 2016 (in Japanese)
  • Kaoru Furumi, Shintaro Mizoguchi, Nanako Niioka, Masashi Imai, Atsushi Kurokawa, "Recognition of Wrist Position While Walking by Using Wearable Triaxial Accelerometers," Proc. ITC-CSCC2016, pp.97-100, Jul., 2016
  • Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa, "Clock Distribution Network with Multiple Source Buffers for Stacked Chips, " IEICE Technical Report, VLD2016-37, pp.167-172, Jun., 2016 (in Japanese)
  • Kaoru Furumi, Masashi Imai, Nanako Niioka, Atsushi Kurokawa, "Thermal Analysis in 3D ICs," IEICE Technical Report, VLD2016-38, pp.173-178, Jun., 2016 (in Japanese)
  • Masashi Imai, Tomohiro Yoneda, "A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches" IEICE Technical Report, VLD2016-39, pp.179-184, Jun., 2016 (in Japanese)
  • Daiki Toyoshima, Atsushi Kurokawa, Masashi Imai, "Tamper Resistant Asynchronous Pipeline Circuits using Random Delay Elements," IEICE Technical Report, VLD2016-40, pp.185-190, Jun., 2016 (in Japanese)
  • Hiroshi Saito, Masashi Imai, Tomohiro Yoneda, "A Task Allocation Method for the DTTR Scheme based on Task Scheduling of Fault Patterns," Proc. ISCAS2016, pp.237-240, May, 2016
  • Tomohiro Yoneda, Naoya Onizawa, Masashi Imai, Takahiro Hanyu, "Power-Gated Single-Track Asynchronous Circuits Using Three-Terminal MTJ-Based Nonvolatile Devices for Energy Harvesting Systems," Proc. Async2016 Fresh ideas track paper, May, 2016
  • Masashi Imai, Tomohiro Yoneda, "Can Asynchronous Circuits Tolerate Hardware Trojan Threat?," Proc. Async2016 Fresh ideas track paper, May, 2016
  • 溝口真太郎, 深瀬政秋, 今井雅, 古見薫, 新岡七奈子, 黒川敦, "ウェアラブルセンサを用いた歩行時の腕の状態認識," 情報処理学会第78回全国大会, 1V-01, Mar., 2016
  • Hiroshi Saito, Masashi Imai, Tomohiro Yoneda, "Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme," IEICE Technical Report, VLD2015-113, No.465, pp.13-18, Feb., 2016 (in Japanese)
  • Kensuke Sato, Masashi Imai, "Research on Development of Dependable Network-on-Chip Platform," IPSJ Tohoku Branch SIG Technical Report, Vol.2015-8, No.B1-1, Feb., 2016 (in Japanese)
  • Kyohei Tereyama, Masashi Imai, "Research on Test Method of Latch-based Asynchronous Circuits," IPSJ Tohoku Branch SIG Technical Report, Vol.2015-8, No. B1-2, Feb., 2016 (in Japanese)

2015

  • Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai, "Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI," IEICE Technical Report, VLD2015-67,DC2015-63, p.189-194, Dec., 2015 (in Japanese)
  • Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai, "Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits," IEICE Technical Report, VLD2015-68,DC2015-64, p.195-200, Dec., 2015 (in Japanese)
  • 齋藤寛, 米田友洋, 今井雅, "DTTR方式によるマルチコアシステムの信頼性向上のためのタスク割り当て手法の検討," 情報処理学会研究報告 Vol.2015-SLDM-172 No.12, pp.63-68, Oct., 2015
  • Kensuke Sato, Hirosahi Saito, Tomohiro Yoneda, Masashi Imai, "A Study on Performance Evaluation of Highly Reliable Multiple-Core Systems," IPSJ SIG Technical Report, Vol.2015-SLDM-172 No.11, pp.57-62, Oct., 2015 (in Japanese)
  • Tomohiro Yoneda, Masashi Imai, "A New Encoding Mechanism for Low Power Inter-Chip Serial Communication in Asynchronous Circuits," Proc. ICCD2015 Poster session, pp.424-427, Oct., 2015
  • Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise, "Dependable Real-Time Task Execution Scheme for a Many-Core Platform," Proc. DFTS2015, pp.198-205, Oct., 2015
  • Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa, "Clock Skew Reduction for Stacked Chips Using Multiple Source Buffers," Proc. ISCIT2015, Oct., 2015
  • Masashi Imai, Tomohiro Yoneda, "Comparing Permanent and Transient Fault Tolerance of Multiple-core based Dependable ECUs," Proc. CARS2015, Sep., 2015
  • Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai, "Performance Comparison between Asynchronous Self-timed Circuits and Synchronous Circuits under Ultra Low Voltage Environment," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), 1A08, Aug., 2015
  • Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai, "Peak Current Reduction Method of Digital Bandpass Filter using Asynchronous MOUSETRAP Pipeline Circuits," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), 1A09, Aug., 2015
  • Kaoru Furumi, Masaaki Fukase, Masashi Imai, Yuuki Miura, Nanako Niioka, Atsushi Kurokawa, "Thermal Analysis with Varying Physical Parameters in 3D ICs," 電気学会 電子・情報・システム部門大会, Aug., 2015
  • 齋藤寛, 米田友洋, 今井雅, "Duplication with Temporary Triple Modular Redundancy and Reconfigurationのためのタスク割り当て手法," DAシンポジウム2015, Aug., 2015
  • Masashi Imai, Tomohiro Yoneda, "Performance Evaluation of Dependable Many-core Systems based on DTTR Method", FTC研究会, Jul., 2015
  • 新岡七奈子, 深瀬政秋, 今井雅, 古見薫, 三浦祐輝, 黒川敦, "三次元集積回路の伝搬遅延とクロストークノイズのモデリング," 第28回 回路とシステムワークショップ, 淡路島, Aug., 2015
  • Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai, "A Study on Function Test of Latch-based Asynchronous Pipeline Circuits," IEICE Technical Report DC2015-19, pp.19-24, Jun., 2015 (in Japanese)
  • Masashi Imai, Tomohiro Yoneda, "Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models," IEICE Technical Report DC2015-20, pp.25-30, Jun., 2015 (in Japanese)
  • Kyohei Terayama, Atsushi Kurokawa, Masashi Imai, "Scan test of latch-based asynchronous pipeline circuits under 2-phase handshaking protocol," Proc. SASIMI15, pp.128-133, Mar. 2015.
  • 小林徹哉, 今井雅, 深瀬政秋, 新岡七奈子, 黒川敦, "ウィンドウベースL逆行列によるTSV間容量抽出," 電子情報通信学会 総合大会 講演論文集, Mar., 2015
  • 星誠, 深瀬政秋, 今井雅, 黒川敦, "高効率遅延セルの実測による性能評価," 電子情報通信学会 総合大会 講演論文集, Mar., 2015
  • Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-aki Fukase, Masashi Imai, and Atsushi Kurokawa, "An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs," Proc. ISQED15, Mar., 2015

2014

  • Masashi Imai, Tomohiro Yoneda, "Energy-and-Performance Efficient Differential Domino Logic Cell Libraries for QDI-model-based Asynchronous Circuits," Proc. APCCAS2014, pp.687-690, Nov., 2014
  • Masayuki Watanabe, ROsely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-aki Fukase, Masashi Imai, Atsushi Kurokawa, "Effect of Substrate Contacts on Reducing Crosstalk Noise between TSVs," Proc. APCCAS2014, pp.763-766, Nov., 2014
  • Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura, "An NoC-based Evaluation Platform for Safety-Critical Automotive Applications," Proc. APCCAS2014, pp.679-682, Nov., 2014
  • Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-aki Fukase, and Atsushi Kurokawa "Impact of On-Chip Interconnects on Vertical Signal Propagation in 3D ICs," Proc. APCCAS2014, pp.607-610, Nov., 2014
  • Masashi Imai, Atsushi Kurokawa, "A Study of Multi-way Arbiter Implementation Methods for High-Speed Communication Asynchronous Circuits," IEEJ Society C, pp.771-776, Sep., 2014 (in Japanese)
  • Kyohei Terayama, Masashi Imai, Atsushi Kurokawa, "Scan Test of Asynchronous Circuits based on 2Phase Handshaking Protocol," IEEJ Society C, pp.765-770, Sep., 2014 (in Japanese)
  • Rosely Karel, Masa-aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, and Atsushi Kurokawa, "Substrate contact effect on TSV-to-TSV coupling," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1A04, Aug. 2014.
  • Nanako Niioka, Masashi Imai, Masa-aki Fukase, Rosely Karel, Tetsuya Kobayashi, and Atsushi Kurokawa, "Modeling and analysis of vertical interconnects in 3D ICs," Proc. Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers (IEEE Student Session), p.1A03, Aug. 2014.
  • Masashi Imai, "Synthesis Library for Asynchronous Fine-grain Pipeline Circuits using DDL Elements," IPSJ DAS2014, pp.73-78, Aug., 2014 (in Japanese)
  • Masashi Imai, (Invited) "The Frontline of Dependable VLSI Systems 2014," WIT2014, Jun., 2014 (in Japanese)
  • Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Tadahiro Hanyu, "High-Throughput Partially Parallel Inter-chip Link Architecture for Asynchronous Multi-Chip NoCs," IEICE Trans on Inf.&Syst., Vol.E97-D, No.6, pp.1545-1556, Jun., 2014
  • Masashi Imai, Tomohiro Yoneda, "Multiple-Clock Multiple-Edge-Triggered Multiple-Bit Flip-flops for Two-Phase Handshaking Asynchronous Circuits," Proc. ISCAS2014, pp.141-144, Jun., 2014
  • Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo, "Construction of Design Environment for Asynchronous Circuits using DDL Cell Library," IEICE Technical Report, CPSY2014-2, pp.3-8, Apr., 2014 (in Japanese)
  • Kyohei Terayama, Masashi Imai, "Scan test of MOUSETRAP pipeline circuit," 2014年電子情報通信学会総合大会, 基礎・境界講演論文集, pp.49, Mar., 2014 (in Japanese)

Imai Labratory

3 Bunkyo-cho,
Hirosaki-shi, Aomori
036-8561, JAPAN

TEL +81-172-39-3637
FAX +81-172-39-3637